1. Field of the Invention
The present invention concerns a modular, hybrid microelectronic structure which permits, notably, high density of integration.
2. Description of the Prior Art
The race to miniaturize electronic functions began in the very early nineteen sixties with the appearance of the first integrated circuits. Considerable advances were made in the designing and manufacture of monolithic integrated circuits. But these advances were less spectacular in the field of connections among integrated circuits.
A specific example will give us a clearer picture: let us consider a module manufactured around 1980, using 80 integrated circuits, encapsulated and mounted on a printed circuit with metallized holes. This module occupied a total area of about 270 cm2. Five years later, it was possible to obtain this same module with only one complex integrated circuit (with the method of monolithic integration of silicon), encapsulated and occupying a total area of 11.2 cm2. The area occupied by this module was thus reduced in a ratio of 1/23. This ratio of reduction in area can be broken down as follows: 1/15.3 for the reduction which can be attributed to silicon alone, and 1/1.5 for the reduction in area which can be attributed to the encapsulation of silicon and to the connections among the integrated circuits.
Thus, in spite of undeniable innovations in the field of encapsulations and connections, the advances made in this field are about ten times less significant than in that of silicon.
If we refer now, for the above-mentioned module, to hybridization on large areas, namely to the direct mounting of the 80 semiconductor chips, corresponding to the above-mentioned 80 integrated circuits, provided with their wiring on an interconnection substrate, an area of 32 cm2 is needed to make the module. Under these conditions, the efficiency of the hybridization, compared with that of monolithic integration of silicon, shows that it is three times higher in terms of the area occupied by the silicon on the interconnection substrate, but three times lower in terms of the reduction in the area of the interconnecion substrate.
Consequently, a major and unavoidable step concerns the hybridization of complex integrated circuits with a prospect of a high gain in area with respect to the printed circuit. Without overlooking complementary difficulties related to electrical testing, this prospect requires a revision of hybridization technologies, especially in the field of substrates.
An aim of the invention is the designing of a hybrid microelectronic structure which copes with these problems by making the best use of the different technologies available for making multiple layers, the choice of the substrates and of the width of the conductors, this width being capable of wide-ranging variation from 250 microns in thick-layer technology to 25 microns in thin-layer technology.
The preponderant factors in the hybrid integration of electronic modules reveal the following "parameters" in decreasing order of importance:
first of all, the "density of integration", which is a relationship between the mean number of connections made, per unit of substrate area, designed for the interconnection of the electronic components. The integration density varies in a ratio of 100/1 for hybrids. It depends greatly on the choice of the silicon chips of the active circuits;
the design rules, characterized by the "pitch" which is the minimum distance, permitted by the technology of the substrate used, between the median lines of two coplanar conductors. This distance is equal to the sum of the minimum permitted width of the conductors and the minimum insulation width required between two adjacent conductors. The pitch varies in a ratio of 10 for the hybrids. It depends greatly on the technology of the interconnection substrate;
the "mean topological degree", namely factor making it possible to take into account the architecture of the interconnections according to an electrical diagram of the hybrid module. The mean topological degree varies between 1 and 2; it is the average number of conductors which radiate out of each interconnection node.
After the characterization of the connection scheme of the "substrate" by these parameters, the design elements of the substrate are deduced therefrom. These are the "number of layers", the "number of vias" or links perpendicular to the plane of the layers to connect these layers together electrically, and the construction technology of the substrate.
The hybrid circuits are designed on an insulating substrate which receives conductors and passive components by printing (silkscreen process) or by etching (photolithography). The active elements, formed by simple or complex integrated circuits, are laid on the substrate and then soldered or bonded. It is said that they are mounted. A distinction is made among three classes of hybrid circuits:
thin-layer (or thin-film) hybrid circuits, in which the superimposed layers are alternately conducting and insulating, are made by photolithography. Each layer has a maximum thickness of 10 microns (the usual abbreviation for a micrometer), the width of the conductors ranges between 10 and 30 microns and the pitch ranges between 30 and 100 microns. These hybrid circuits are limited by the small number of superimposed insulating layers that can be made (generally not more than five layers) because of technological difficulties and the resultant cost;
thick-layer (or thick-film) hybrid circuits in which the superimposed and alternately conducting and insulating layers are obtained by successive silkscreen process and baking operations. Each layer has a thickness of more than 10 microns. The width of the conductor is generally 250 microns, and the pitch is 500 microns. The limitations of these hybrid circuits lie in the maximum number (hardly more than six) of superimposed, insulated conducting layers and in the difficulty of wiring the connected semiconductor chips with poor planeity of the silkscreen printed elements. When the circuits are made of ceramic, it is practically impossible to make interconections between layers by vias;
thick-layer hybrid circuits in which the conducting layers are obtained by silkscreen printing on insulating layers, which are sheets of ceramic placed on top of one another, pressed, and then baked together all at once, after the drilling of interconnection vias between the layers and the silkscreen printing of the conductors. These ceramic integrated circuits are said to be "co-baked". Since the number of insulating layers no longer represents a constraint, the limitations of these hybrid circuits arise out of the constraints related to the wiring of the semiconductor chips with a great number of input/output pads, the interval of which is far smaller than the minimum pitch of the circuits printed by silkscreen process (300 microns). The active elements used are placed on one or both faces of the co-baked type multilayer substrate with thick layers. The active elements are, for example, encapsulated, monolithic integrated circuits, and are in the form of semiconductor chips encapsulated collectively (standard hybrid circuits).
Furthermore, it is necessary, in thin multilayer hybrid circuit technology, to use circuits with very high integration density comprising, in particular, at least one semiconductor chip mounted on the thin multilayer substrate having a great number (possibly more than 100) of inputs/outputs, the interval of which is far smaller than the minimum pitch (about 300 microns) permitted by the state of the art for silkscreen printing in thick-layer technologies. The essential constraints imposed by these thin multilayer circuits are as follows:
the need for a substrate acting as a mechanical support for the thin layer; a ceramic material such as alumina is often used;
the making of more than three layers proves to be difficult and prohibitively costly;
the connection has to be made by wire connections between the thin-layer substrate and the outside;
the assembly has to be protected from the environment, especially from humidity, by being placed in a package through which the external connections system has to be provided.
An object of the invention is to reconcile thin-layer technologies with thick-layer technologies to improve the performance characteristics of a hybrid structure in terms of density of integration, notably when the circuits comprise semiconductor chips with a great number of inputs and outputs. It shall be seen further below that other advantages result from the invention, among others:
better local adaptation to the different densities of integration of the mounted circuits;
elimination of wiring at the edge of the thin-layer hybrid module;
optimum reduction of the number of thin layers;
optimum reduction of the number of conductive layers of the thick layers;
decoupling of the supplies made easier, without loss of area for the connections;
easy discharge of heat into the environment;
easy assembly and dismantling of the hybrid module with external interconnections which can be mechanically separated from the module.